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hexfet power mosfet hexfet ? is a registered trademark of international rectifier. * qualification standards can be found at http://www.irf.com/ gds gate drain source v dss 40v r ds(on) typ. 1.65m max. 1.98m i d (silicon limited) 211a i d (package limited) 100a

applications electric power steering (eps) battery switch start/stop micro hybrid heavy loads dc-dc converter descriptionspecifically designed for automotive applications, this hexfet? power mosfet utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. additional features of this design are a 175c junction operating temperature, fast switching speed and improved repetitive avalanche rating. these features combine to make this design an extremely efficient and reliable device for use in automotive applications and wide variety of other applications. features advanced process technology new ultra low on-resistance 175c operating temperature fast switching repetitive avalanche allowed up to tjmax lead-free, rohs compliant automotive qualified * absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. ambient temperature (t a ) is 25c, unless otherwise specified. s d g d-pak auirfr8405 i-pak auirfu8405 d s d g symbol parameter units i d @ t c = 25c i d @ t c = 100c i d @ t c = 25c continuous drain current, v gs @ 10v (package limited) i dm pulsed drain current p d @t c = 25c maximum power dissipation w linear derating factor w/c v gs gate-to-source voltage v t j operating junction and t stg storage temperature range soldering temperature, for 10 seconds (1.6mm from case) avalanche characteristics e as (thermally limited) single pulse avalanche energy e as (tested) single pulse avalanche energy tested value i ar avalanche current a e ar repetitive avalanche energy mj thermal resistance symbol parameter typ. max. units r jc junction-to-case CCC 0.92 r ja junction-to-ambient (pcb mount) CCC 50 r ja junction-to-ambient CCC 110 continuous drain current, v gs @ 10v (silicon limited) continuous drain current, v gs @ 10v (silicon limited) c/w mj 208 see fig. 14, 15, 24a, 24b 163 c a 300 -55 to + 175 20 1.1 max. 211 150 804 100 256

!" form quantity tube 75 auirfr8405 tape and reel 2000 auirfr8405tr tape and reel left 3000 AUIRFR8405TRL tape and reel right 3000 auirfr8405trr auirfu8405 ipak tube 75 auirfu8405 auirfr8405 dpak complete part number package type base part number standard pack downloaded from: http:///

!" s d g calculated continuous current based on maximum allowable junction temperature. bond wire current limit is 100a

. note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements.

repetitive rating; pulse width limited by max. junction temperature. limited by t jmax , starting t j = 25c, l = 0.051mh, r g = 50 , i as = 90a, v gs =10v. part not recommended for use above this value. i sd 90a, di/dt 1304a/ s, v dd v (br)dss , t j 175c. pulse width 400 s; duty cycle 2%. c oss eff. (tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss . c oss eff. (er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 to 80% v dss . when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994.

all ac and dc test condition based on old package limitation current = 90a. static @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units v (br)dss drain-to-source breakdown voltage 40 CCC CCC v v (br)dss / t j breakdown voltage temp. coefficient CCC 0.03 CCC v/c r ds(on) static drain-to-source on-resistance CCC 1.65 1.98 v gs(th) gate threshold voltage 2.2 3.0 3.9 v i dss drain-to-source leakage current CCC CCC 1.0 CCC CCC 150 i gss gate-to-source forward leakage CCC CCC 100 gate-to-source reverse leakage CCC CCC -100 r g internal gate resistance CCC 2.3 CCC dynamic @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units gfs forward transconductance 294 CCC CCC s q g total gate charge CCC 103 155 q gs gate-to-source charge CCC 26 CCC q gd gate-to-drain ("miller") charge CCC 38 CCC q sync total gate charge sync. (q g - q gd ) CCC 65 CCC t d(on) turn-on delay time CCC 12 CCC t r rise time CCC 80 CCC t d(off) turn-off delay time CCC 51 CCC t f fall time CCC 51 CCC c iss input capacitance CCC 5171 CCC c oss output capacitance CCC 770 CCC c rss reverse transfer capacitance CCC 523 CCC c oss eff. (er) effective output capacitance (energy related) CCC 939 CCC c oss eff. (tr) effective output capacitance (time related) CCC 1054 CCC diode characteristics symbol parameter min. typ. max. units i s continuous source current (body diode) i sm pulsed source current (body diode) v sd diode forward voltage CCC 0.9 1.3 v dv/dt peak diode recovery CCC 2.1 CCC v/ns t rr reverse recovery time CCC 28 CCC t j = 25c v r = 34v, CCC 29 CCC t j = 125c i f = 90a** q rr reverse recovery charge CCC 19 CCC t j = 25c di/dt = 100a/ s CCC 20 CCC t j = 125c i rrm reverse recovery current CCC 1.1 CCC a t j = 25c ns nc a CCCCCC CCCCCC 211 804 m a na nc ns pf conditions v ds = 10v, i d = 90a** i d = 90a ** v gs = 20v v gs = -20v v ds = 40v, v gs = 0v, t j = 125c v ds =20v conditions v gs = 10v v gs = 0v v ds = 25v ? = 1.0 mhz, see fig. 5 v gs = 0v, v ds = 0v to 32v , see fig. 11 i d = 90a** r g = 2.7 v gs = 10v conditions v gs = 0v, i d = 250 a reference to 25c, i d = 5ma v gs = 10v, i d = 90a** v ds = v gs , i d = 100 a v ds = 40v, v gs = 0v t j = 175c, i s = 90a**, v ds = 40v v dd = 26v i d = 90a **, v ds =0v, v gs = 10v t j = 25c, i s = 90a** , v gs = 0v integral reverse p-n junction diode. v gs = 0v, v ds = 0v to 32v mosfet symbol showing the downloaded from: http:///

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!" fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.8v 60 s pulse width tj = 25c 4.8v 0.1 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60 s pulse width tj = 175c 4.8v vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.8v 2 3 4 5 6 7 8 v gs , gate-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t j = 25c t j = 175c v ds = 10v 60 s pulse width -60 -20 20 60 100 140 180 t j , junction temperature (c) 0.4 0.8 1.2 1.6 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 90a v gs = 10v 0.1 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 20 40 60 80 100 120 140 q g , total gate charge (nc) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 32v v ds = 20v i d = 90a downloaded from: http:///

!" fig 8. maximum safe operating area fig 10. drain-to-source breakdown voltage fig 7. typical source-drain diode forward voltage fig 11. typical c oss stored energy fig 9. maximum drain current vs. case temperature fig 12. maximum avalanche energy vs. draincurrent 0.2 0.6 1.0 1.4 1.8 v sd , source-to-drain voltage (v) 0.1 1 10 100 1000 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v -60 -20 20 60 100 140 180 t j , temperature ( c ) 40 41 42 43 44 45 46 47 48 v ( b r ) d s s , d r a i n - t o - s o u r c e b r e a k d o w n v o l t a g e ( v ) id = 5.0ma -5 0 5 10 15 20 25 30 35 40 45 v ds, drain-to-source voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 e n e r g y ( j ) 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 100 200 300 400 500 600 700 800 900 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 18a 37a bottom 90a 25 50 75 100 125 150 175 t c , case temperature (c) 0 30 60 90 120 150 180 210 240 i d , d r a i n c u r r e n t ( a ) limited by package 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100 sec dc limited by package downloaded from: http:///

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!" fig 13. maximum effective transient thermal impedance, junction-to-case fig 14. typical avalanche current vs.pulsewidth fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15(for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far inexcess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 24a, 24b.4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15).t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figures 13) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.0001 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) c / w 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? j = 25c and tstart = 150c. 0.01 allowed avalanche current vs avalanche pulsewidth, tav, assuming tj = 150c and tstart =25c (single pulse) 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 50 100 150 200 250 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1.0% duty cycle i d = 90a downloaded from: http:///

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fig 17. threshold voltage vs. temperature

fig 16. on-resistance vs. gate voltage 4 6 8 10 12 14 16 18 20 v gs, gate -to -source voltage (v) 0.0 2.0 4.0 6.0 8.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( m ) i d = 90a t j = 25c t j = 125c -75 -25 25 75 125 175 225 t j , temperature ( c ) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) id = 100 a id = 250 a id = 1.0ma id = 1.0a 0 200 400 600 800 1000 di f /dt (a/ s) 0 1 2 3 4 5 6 7 8 9 i r r m ( a ) i f = 36a v r = 34v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/ s) 10 20 30 40 50 60 70 80 90 100 110 120 q r r ( n c ) i f = 36a v r = 34v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/ s) 0 1 2 3 4 5 6 7 8 i r r m ( a ) i f = 90a v r = 34v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/ s) 0 20 40 60 80 100 q r r ( n c ) i f = 90a v r = 34v t j = 25c t j = 125c downloaded from: http:///

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!" fig 22. typical on-resistance vs. drain current 0 100 200 300 400 500 i d , drain current (a) 0.0 3.0 6.0 9.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( m ) vgs = 5.5v vgs = 6.0v vgs = 7.0v vgs = 8.0v vgs = 10v downloaded from: http:///

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!" fig 25a. switching time test circuit fig 25b. switching time waveforms fig 24b. unclamped inductive waveforms fig 24a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 26a. gate charge test circuit fig 26b. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr fig 23. for n-channel hexfet power mosfets
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p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period ! "#!$ %%
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) tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl notes : 1. controlling dimension : millimeter. 2. all dimensions are shown in millimeters ( inches ). 3. outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch

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qualification information ? 3l-d-pak msl1 i-pak n/a qualification level automotive (per aec-q101) comments: this part number(s) passed automotive qualification. irs industrial and consumer qualification level is granted by extension of the higher automotive level. charged device model class c5 (+/- 2000) ?? aec-q101-005 moisture sensitivity level rohs compliant yes esd machine model class m3 (+/- 400) ?? aec-q101-002 human body model class h1c (+/- 2000) ?? aec-q101-001 downloaded from: http:///

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!" date comments ? corrected label on soa curve fig 8 on page 4. ? updated package outline on page 9 & 10 revision history 10/17/2014 downloaded from: http:///

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